Memory devices have memory arrays with large numbers of individual memory cells. During fabrication of the memory arrays, or in subsequent packaging of the memory, it is possible for cell failures to be introduced in the memory. Furthermore, errors can occur in processing data in and out if memory cells. In some cases, introduction of such failures can result in the need to discard the device entirely.
Consequently, many memory devices utilize error correction code (ECC) or an ECC mode to compensate for cell failures in memory arrays. The ECC mode is used to generate parity codes, which are stored in a parity memory, to detect, and in some cases correct, errors or failures in memory cells. In some cases, ECC circuitry is built onto a memory chip in order to achieve superior quality for a customer.
Typically, memory devices have a memory array within which specific areas are dedicated to store ECC parity bits. For some applications of these memory devices the ECC mode will be used and for others it will not. In applications where the ECC mode is not used, the area of the memory array dedicated to storing ECC parity bits unnecessarily draws and uses current. For these and other reasons, there is a need for the present invention.